Contains the formal syntax and semantics of all Verilog HDL constructs; the formal syntax and semantics of Standard Delay Format (SDF) constructs; simulation system tasks and functions, such as text output display commands; compiler directives, such as text substitution macros and simulation time scaling; the Programming Language Interface (PLI) binding mechanism; the formal syntax and semantics of access routines, task/function routines, and Verilog procedural interface routines; informative usage examples; informative delay model for SDF; listings of header files for PLI. This publication has the status of a double logo IEEE/IEC standard